A semiconductor package fabrication process, as described in U.S. Pat. No. 6,087,202 (the disclosure of which is hereby incorporated by reference), comprises bonding chips on a front face of a rigid electrical connection substrate, connecting the chips to the front face of the substrate via electrical connection wires, injection-over molding of blocks of encapsulation material on the front face of the substrate by embedding small numbers of chips per block and the corresponding electrical connection wires, and dicing the assembly thus formed in order to singulate semiconductor packages.